1. Field of the Invention
The present invention relates to a substrate processing apparatus for and a substrate processing method of forming a coating film pattern on any of a variety of substrates such as a semiconductor wafer, a glass substrate for liquid-crystal-display-panel, a glass substrate for plasma-display-panel, a photo mask substrate, an optical-disk substrate, a magnetic-disk substrate, a magneto-optical-disk substrate, a print-circuit board and the like.
2. Description of Related Art
The process of forming multi-layer wirings on the surface of a semiconductor wafer comprises: a step of coating, with a photosensitive SOD (Spin on dielectric) solution, a semiconductor wafer having wiring patterns of aluminum or copper formed thereon, and drying the SOD solution to form an SOD film; a CMP (chemical and mechanical polishing) step of flattening the SOD film; a step of executing an exposure processing and a developing processing on the SOD film thus flattened, thereby to form openings for interlayer wirings; and a step of embedding wiring metals in the openings.
There are cases where the SOD film is formed with the use of,instead of a photo sensitive SOD solution, a normal SOD solution to which photosensitivity is not being given. In such a case, the SOD film is first flattened by a CMP step, a resist film is then formed on this SOD film, an exposure processing and a developing processing are then executed on this resist film to form a pattern, and the SOD film is then etched with the resist film serving as an etching mask. Thus, openings for interlayer wirings are formed in the SOD film.
The SOD film flattening processing is required for precisely executing an exposure processing on a photosensitive SOD film or a resist film in a desired pattern by an exposure unit. More specifically, when the SOD film surface is uneven and the pattern to be formed is very fine, this fine pattern is not properly focused on the SOD film surface or the resist film surface, so that the pattern image becomes vague or obscure.
When forming a fine-pattern resist film, the focusing range (depth of field) at the time of exposure is narrow. The resist film thickness is therefore required to be thin. In this connection, the CMP step is inevitable before the resist film is coated.
At the CMP step, however, contamination occurs due to a polishing agent. Accordingly, a so-called post-CMP cleaning is required. This disadvantageously not only takes much processing time, but also increases the production cost. Further, if cleaning is not sufficient, the polishing agent contamination remains on the semiconductor wafer surface. This exerts adverse effects on the subsequent process, thus disadvantageously lowering the production yield.
Further, due to the characteristics of a polishing processing by the CMP step, there is a tendency that the SOD film height from the semiconductor wafer surface is large at the peripheral edge of the wafer and small at the center portion thereof. Accordingly, the flatness cannot be assured for a large-size semiconductor wafer (having a diameter of, for example, 300 mm).